Memory, such as dynamic random access memory (DRAM), is used in a multitude of electronics systems (e.g., portable computers, desktop computers, server systems, mobile devices, etc.) and has gone through several advancements over the years. For example, double data rate DRAM (DDRAM) was as first progression from the initial DRAM and operates at double the rate. Since then, DDRAM has also gone through a series of development milestones with each milestone improving the performance. This progression of development resulted in sequentially numbered DDRAM, e.g. DDR2, DDR3, and DDR4 development iterations. The DDR4 iteration has introduced new operating modes due to the ever increasing clock speeds of current computing systems employing DDR memories.
As DRAM's target CLK frequency continues to increase, the CAS latency control becomes more difficult due to the fact that it requires clock domain crossing from the external CLK to the internal clock (e.g., delay locked loop (DLL) clock) in a short CLK period (e.g., “fast” tCK). Also, to be competitive in the low-power DRAM market, it may be desirable to minimize unnecessary clocking when circuitry is not in use. CAS latency control scheme generally involves two clock domains where a command (read command or ODT command) is captured by a CLK-domain clock and data related to the command is provided according to the variable DLL-domain clock. In order to provide the data on time at the output PAD, the command in the CLK domain may be converted to the DLLCLK domain and also may be delayed by CAS latency (CL) and/or CAS Write Latency (CWL). Since the phase relationship between CLK and DLLCLK is variable, depending on tCK and PVT corners, it may be desirable to achieve smooth domain crossing with accurate CL calculation, especially at fast tCK operation.